1. Field of the Invention
The present invention relates to a clock control type information processing apparatus for switching a clock frequency and for controlling stop and restart of the clock signals supplied by clock generating units according to the load states of peripheral processing units and a central processing unit.
2. Description of the Prior Art
In an information processing apparatus, especially a portable personal computer, an important consideration is how to maintain the operating time longer under the environment for portable usage without being connected to a power adapter, that is, how to maintain the operating time longer by inner battery driving. Considering today's environmental issue, not only for a portable personal computer but also for all information processing apparatuses, it is important to make the electric power consumption of the units as low as possible. For example, since the electric power consumption of an information processing apparatus using CMOS logic becomes higher when the clock frequency of the device becomes higher, it has been suggested to reduce the clock frequency of the device, or to temporally stop the clock under a predetermined condition.
For example, Japanese Laid-open Publication 6-83756 discloses a clock control method as a system for reducing the electric power consumption of information processing apparatuses. The clock control method stops the clock according to the operating state for every function block, and starts the clock according to the control signal for operating the function block. FIG. 9 shows a conventional information processing apparatus for reducing the electric power consumption described in Japanese Laid-open Publication 6-83756.
FIG. 9 is a block diagram showing an example of a data processing apparatus illustrated in Japanese Laid-open Publication 6-83756. In FIG. 9, the data processing apparatus includes a micro processor 101, DMA unit 102, a memory 103, two peripheral processing units 31 and 32, an address bus (A) 105, a data bus (D) 106 and a control bus (C) 107 for connecting peripheral processing unit 31 or 32 with the micro processor 101, the DMA unit 102, and the memory 103. When DMA request signal REQ0 is output from the peripheral processing unit 31, the DMA unit 102 requests permission for DMA to the micro processor 101. When the permission is given, the DMA unit 102 transfers the data from the memory 103 to the peripheral processing unit 31 and from the peripheral processing unit 31 to the memory 103. This process also is applied to the peripheral processing unit 32 as well.
The micro processor 101 carries out the data processing according to the programmed contents by sending and receiving data between the memory 103 and the peripheral processing unit 31 or 32 via the address bus (A) 105, the data bus (D) 106 and the control bus (C) 107. When the DMA request signal HREQ is output from the DMA unit 102, the micro processor 101 stops the processing to generate DMA permission signal HACK and supplies it to the DMA unit 102.
FIG. 10 shows the DMA unit 102, which includes a transfer request control unit 111, a clock control unit 112, first channel control unit 113 and a second channel control unit 114. The DMA unit 102 outputs the DMA request signal HREQ to the micro processor 101 when the DMA request signal REQ0 or REQ1 are output from the peripheral processing unit 31 or 32, respectively. The DMA unit 102 supplies the clock signal to any one of the first channel control unit 113 and the second channel control unit 114 to transfer the data from the memory 103 to the peripheral processing unit 31 or 32, or from the peripheral processing unit 31 or 32 to the memory 103, according to the DMA permission signal HACK output from the micro processor 101.
The transfer request control unit 111 operates the clock control unit 112 so that the clock control unit 112 supplies the first clock signal only to the first channel control unit 113 when the DMA request signal REQ0 for requesting the DMA transfer of the first channel's side is output from the peripheral processing unit 31. The transfer request control unit 111 operates the clock control unit 112 so that the clock control unit 112 supplies the second clock signal only to the second channel control unit 114 when the DMA request signal REQ1 for requesting the DMA transfer of the second channel's side is output from the peripheral processing unit 32. On the other hand, the transfer request control unit 111 operates the clock control unit 112 so that the clock control unit 112 stops output of the first clock signal corresponding to the first channel control unit 113 and the second clock signal corresponding to the second channel control unit 114, respectively, when the DMA request signal REQ0 and REQ1 are not output from the peripheral processing unit 31 or 32.
When the transfer request control unit 111 receives the signal indicating the transfer termination from the first channel control unit 113 and the second channel control unit 114, the transfer request control unit 111 operates the clock control unit 112 so that the clock control unit 112 stops the clock signals supplied to the first channel control unit 113 or the second channel control unit 114.
A method for controlling the clock frequency according to the processing load state of the central processing unit which executes the program is also suggested.
As mentioned above in connection with the conventional information processing apparatus, there are the following problems. First, in the information processing apparatus for controlling the clock according to the processing load of the central processing unit, the clock signals supplied to the peripheral processing units can not be stopped or can not be reduced even when the peripheral processing units are inactive, if the central processing unit executes the program with high processing load. The construction described in the Japanese Laid-open Publication 6-83756 requires a detector for detecting an operating state for every function block. In other words, the increase of the function blocks causes the increase of the circuits for detecting the operating states. Therefore, the construction needs increased electric power consumption as a whole system.